Achieving high and stable manufacture yields is important for integrated circuit products to meet quality, reliability and profitability objectives. Yields, however, tend to be significantly lower than acceptable when a new manufacturing process is introduced, or a new design is introduced to a mature manufacturing process. Yield learning or analysis can be employed to ramp up the initial low yield.
A critical goal in a yield analysis process is to identify root causes of the yield loss. Some yield analysis techniques extract root causes from volume scan diagnosis results. Based on design information, test patterns used to detect the failure, and failure data, scan diagnosis can identify specific locations in a design that are likely to explain the failure data. Scan diagnosis results, however, are usually not definite. The ambiguity is two-fold: First, the scan diagnosis often identifies multiple locations (referred to as suspects hereinafter) for the observed defective logical behavior; second, each suspect may be associated with multiple potential defect root causes.
Various methods have been employed to extract true or at least probable defect root cause(s) from “noisy” scan diagnosis reports. One method employs an iterative learning algorithm to derive feature failure probabilities. Here, a feature is a layout configuration in the design with unique characteristics such as side-to-side bridges on metal layer 3. A feature having a high feature failure probability could be a root cause of the yield loss. In this method, the feature failure probability for a feature is expressed by an equation that includes feature failure probabilities for all of the features. Starting with initial guesses, feature failure probabilities are calculated iteratively until converging to a solution. The derived feature failure probabilities show which features are likely to be yield limiters.
Another method called zonal analysis manages the diagnosis noise by dividing a wafer into a set of zones. For example, a zone map may include a center zone, a middle zone and an outer zone. If defects are of random nature, Pareto distribution for various features is expected to be similar across the zone map of failing wafers. If a feature has a higher occurrence in one zone than in the rest, that feature may be treated as the root cause.
More recently, a new method, referred to as root cause deconvolution, is developed based on the Bayesian probability analysis. The method uses the Bayesian model to formulate the probability of observing a set of diagnosis results for a given feature failure distribution. An expectation-maximization process is performed to derive the most likely feature failure distribution.
No matter which of the above methods is used, the knowledge of features that are potential root causes is required. Potential root causes may be derived, for example, based on available design-for-manufacture (DFM) rules or heuristics. This may not be sufficient however, because a new manufacturing process or a new design may suffer yield losses caused by previously-unknown root causes. It is thus desirable to search for new methods for identifying potential root causes.